1. Field of the Invention
The present invention relates to microelectronic device fabrication, and more particularly, to a method of forming tungsten or tungsten silicide layers for use in gate metallizations and local interconnects in a semiconductor integrated circuit.
2. Description of the Related Technology
In microelectronic devices common in the art, a field effect transistor 10 is formed in a semiconductor 11 by interposing a gate 12 of the transistor between heavily doped regions comprising the source 14 and drain 16 of the transistor as shown in FIG. 1. In older semiconductor devices, the gate 12 comprised doped polycrystalline silicon (poly) over the gate dielectric 20. However, as the dimensions of transistors and their interconnections have decreased into the submicron region, the high resistivity of doped poly adversely impacts the switching speed of field effect transistors 10. Thus, to increase the switching speed of a transistor 10, semiconductor manufacturers use a multilayer structure 18 including a metallic layer, such as tungsten (W) or tungsten silicide (WSi2), to reduce the resistivity of gates 12 and local interconnect lines so as to increase the operating speed of circuits formed from interconnected transistors. Thus, the gate 12 of a current transistor 10 typically comprises a multilayer structure 18 on top of a thin silicon oxide layer 20 in contact with the silicon semiconductor 11. The multilayer structure 18 comprises a doped poly layer 22 in contact with the silicon oxide layer 20 and a metallic layer 24 comprising W or WSi2 in contact with the poly layer 22.
During the formation of the microelectronic device, a metallic W or WSi2 layer may be deposited either selectively or nonselectively. In U.S. Pat. No. 4,913,929, Moslehi, et al., disclose several selective and nonselective methods for depositing a W layer using a cold wall single wafer thermal/microwave remote plasma multiprocessing reactor. Moreover, as described by Leusink, et al., in J. Appl. Phys. 72, 490 (1992), selective deposition of W or WSi2 proceeds by the following well known chemical reactions:
2WF6(g)+3Si(s)xe2x86x922W(s)+3SiF4(g)xe2x80x83xe2x80x83(1)
WF6(g)+3Si(s)xe2x86x92W(s)+3SiF2(g)xe2x80x83xe2x80x83(2)
W(s)+2Si(s)xe2x86x92WSi2xe2x80x83xe2x80x83(3)
2WF6(g)+7Si(s)xe2x86x922WSi2(s)+3SiF4(g)xe2x80x83xe2x80x83(4)
Reactions 1 and 2 describe the formation of tungsten. After the tungsten has been formed by either reaction 1 or 2, it can react further with the underlying Si to form WSi2 (reaction 3). Reaction 4 describes the direct formation of WSi2. Thus, the basic reaction is the silicon (Si) reduction of tungsten hexafluoride (WF6) gas, a displacement reaction where exposed Si is converted to a solid layer of W thereby releasing the displaced Si in the volatile gases SiF2 and SiF4. In contrast to nonselective or blanket depositions, these reactions cause selective deposition of W because only those Si regions exposed to WF6 on the semiconductor 11 react to form a deposited W layer. There is no conversion to W of regions of the semiconductor 11 having exposed regions comprising materials other than Si, such as silicon oxide (SiO2) or silicon nitride (Si3N4).
According to reactions (1) and (2), every nanometer of W formed consumes approximately two nanometers of the exposed Si. Thus, as noted by Leusink, et al., the Si reduction of WF6 should be suppressed as the etching of exposed Si, such as source or drain regions, is an undesired result. To prevent or reduce undesired etching of exposed Si regions, combinations of WF6 gas and reducing agents, such as the gases H2, SiH4 or GeH4, have been used for the chemical vapor deposition (CVD) of W. Currently, tungsten CVD by WF6/H2 or WF6/SiH4 are the preferred methods used in the microelectronics industry. However, in IEEE Trans. Electron Devices, 37, 577 (1990), Kobayashi, et al., describe applying the selective deposition of W to form a W contact (plug) by substitution of undoped poly by W. FIG. 2a illustrates a cross sectional view of a semiconductor wafer prepared for the substitution of undoped poly by W. An oxide layer 32 resides on the silicon substrate 30. A barrier layer 34 comprising titanium nitride (TiN) resides on the silicon oxide layer 32 and within the contact aperture 38, where the TiN barrier layer 34 contacts the silicon substrate 30. Lastly, a conformal poly layer 36 is deposited over the TiN barrier layer 34.
Referring now to FIG. 2b, an etch back of the poly layer 36 is performed to remove poly from the TiN barrier layer 34. Note that the etch back step slightly over etches the poly layer 34 so that the remaining poly 36 is slightly recessed within the aperture 38. Referring now to FIG. 2c, a thin chemical oxide layer 40 is formed over the poly 36 within the aperture 38. This chemical oxide layer 40 enhances the subsequent selective deposition of W. Lastly, substitution of poly 36 by W using WF6 gas occurs to form a W plug 42 as shown in FIG. 2d. Note that the entire volume of poly 36 (FIG. 2c) within the contact aperture 38 is replaced by W so as to form a W plug 42. The TiN barrier layer 34 serves to stop the substitution of Si by W during the selective deposition of a contact. Moreover, this technique is also well adapted to via fills in multilevel metal layer interconnections. However, the TiN barrier layer 34 is not needed in a via fill process as the lower level metal serves to stop the Si substitution by W. Thus, selective deposition of W techniques have found only limited application in contact formation and via fill because of the desire to avoid consumption of exposed Si regions in other device fabrication applications.
Although Moslehi, et al., disclose in U.S. Pat. No. 4,913,929 that several wafer processing steps can be done sequentially in a single reactor, semiconductor manufacturers currently use multiple reactors of significantly different configuration to form and interconnect the many layers needed in a microelectronic device. For example, a manufacturer may use a cluster tool, such as an Applied Materials Centura, having a reactor chamber dedicated to the deposition of poly and also having a reactor chamber of significantly different configuration dedicated to the deposition of WSi2. The present art for tungsten silicide formation uses a gas mixture consisting of tungsten hexafluoride and silane or dichlorosilane. The tungsten silicide deposits according to the following reactions:
2WF6+7SiH4xe2x86x922WSi2+2SiF4+14H2xe2x80x83xe2x80x83(5)
2WF6+10SiH2Cl2xe2x86x922WSi2+3SiF4+3SiCl4+8HCl+6H2xe2x80x83xe2x80x83(6)
The nonselective WSi2 deposition results in deposition of WSi2 on the reactor walls and other areas exposed to the WF6 and SiH4 gas. Thus, this WSi2 reactor chamber requires downtime for frequent etching (cleaning) to remove the WSi2 buildup on exposed areas.
The use of multiple different reactors often results from a strategy to prevent incompatible chemical reactions and materials produced during the formation of a prior layer from impacting the formation of a current or subsequent layer in the same reactor. This strategy is of critical importance to a semiconductor manufacturer as minuscule amounts of impurities in any single layer of a microelectronic device often result in device failures and scrap. At the same time, however, the need for multiple reactors of different configuration creates substantial operational issues in addition to the significant capital funds required to procure multiple different reactors. For example, the manufacturer has to maintain spares for each of the multiple reactor configurations used in its factory at a considerable cost for spares inventory, warehousing and personnel to manage spares.
To improve their operations, microelectronic device manufacturers require fabrication methods and systems that enable them to perform multiple processing steps in reactor chambers of substantially similar configuration. Similarly, manufacturers require fabrication methods and systems that enable them to reduce the amount of cleanroom floorspace needed by fabrication equipment. Manufacturers likewise require fabrication methods and systems that reduce the amount of equipment downtime for cleaning and maintenance. In addition, manufacturers require fabrication methods and systems that reduce the need to manage a substantial number of different spares and consumables inventories for multiple different reactors. Moreover, manufacturers require fabrication methods and systems that facilitate continuous improvement of their fabrication equipment by their equipment vendors. Lastly, manufacturers require fabrication methods and systems that reduce the number of multiple different reactors so as to also reduce the amount of capital finds needed to procure fabrication equipment.
The present invention enables manufacturers to improve their operations by applying an integrated process to deposit poly or amorphous silicon and tungsten or tungsten silicide for use in the formation of multilayer gate metallizations in semiconductor integrated circuits. In contrast to present methods that produce tungsten or tungsten silicide deposits on reactor walls and other exposed areas, the present invention eliminates the need to use different reactors to form poly, tungsten and tungsten silicide layers in a gate structure and reduces the risk of contamination from reactor deposits and incompatible materials. The present invention likewise reduces equipment downtime for cleaning and maintenance operations associated with deposits on reactor walls and other exposed areas thereby improving equipment throughput. Moreover, the present invention permits a manufacturer to form the poly, tungsten and tungsten silicide layers of a gate structure in the same reactor, in another reactor of substantially similar configuration to the reactor used to form the poly layer or in a reaction chamber of a cluster tool of substantially similar configuration to the reactor chamber used to form the poly layer. Thus, using the present invention, manufacturers can reduce the costs of procuring a variety of different reactors to form these layers. Similarly, manufacturers can reduce the cleanroom floorspace occupied by a variety of different reactors to deposit poly, tungsten and tungsten silicide. In addition, the present invention reduces the associated costs to manage spares inventories related to a variety of different reactors. Lastly, in contrast to structures fabricated using conventional techniques, the present invention produces gate metallization structures with improved adhesion between the tungsten or tungsten silicide layers and the poly layer thereby enabling the reduction of gate dimensions to increase circuit densities.
One aspect of the present invention includes a method of forming a gate in a semiconductor integrated circuit comprising the steps of forming a silicon layer over a gate dielectric layer on a substrate and forming a tungsten layer by converting a portion of said silicon layer to tungsten.
Another aspect of the present invention includes a method of forming a gate in a semiconductor integrated circuit device comprising the steps of forming a silicon layer over a gate dielectric layer on a substrate, forming a tungsten layer by converting a portion of said silicon layer to tungsten and annealing said substrate so as to convert a portion of said tungsten layer to a tungsten silicide layer.
Yet another aspect of the present invention includes a method of forming a gate in a semiconductor integrated circuit device comprising the steps of forming a silicon layer over a gate dielectric layer on a substrate and forming a tungsten silicide layer by converting a portion of said silicon layer to tungsten silicide.